A flash memory device generally includes a cell transistor that has a tunnel oxide layer pattern, a first gate pattern serving as a floating gate, a dielectric layer pattern and a second gate pattern serving as a control gate. When a voltage is applied to the control gate, electrons may be injected into the floating gate to store charge therein, which represents data in the flash memory device. A flash memory device may be improved by reducing the loss of the voltage applied to the floating gate. The loss of the voltage applied to the floating gate may be reduced for example, by improving the capacitive coupling ratio of the device.
As the feature sizes of semiconductor devices continuously decrease, the dielectric layer pattern of a flash memory device may occupy a smaller and smaller area. When the dielectric layer pattern has a small area, the capacitive coupling ratio of the flash memory device may also decrease. Thus, to maintain the capacitive coupling ratio of the flash memory device, it may be desirable to form the dielectric layer pattern with a reduced thickness.
However, as the thickness of the dielectric layer pattern is reduced, leakage current between the floating gate and the control gate may increase, which may reduce the capacitive coupling ratio of the flash memory device. Such leakage current may also impair the electrical characteristics of flash memory devices.
To reduce leakage current and to improve the capacitive coupling ratio, a high-k dielectric material has been employed as the dielectric layer of a flash memory device. Methods of forming a dielectric layer using a high-k dielectric material are disclosed, for example, in U.S. Pat. No. 6,642,573 issued to Halliyal et al., and/or U.S. Pat. No. 6,617,639 issued to Wang et al., the disclosures of which are incorporated herein by reference in their entireties.
When a dielectric layer including a high-k dielectric material is employed together with a control gate of polysilicon doped with N-type impurities, the work function of the control gate may be too low, such that tunneling current between the dielectric layer and the control gate may increase. Hence, a metal having a high work function may be employed for the control gate instead of polysilicon doped with the N-type impurities in order to reduce the tunneling current. However, when the control gate is formed using a metal having a high work function, some problems may result, as described below.
FIG. 1 is a schematic cross-sectional view illustrating conventional methods of forming a semiconductor device. As shown therein, a tunnel oxide layer 12 and a polysilicon layer 14 are sequentially formed on a semiconductor substrate 10 including a cell region 11 and a peripheral circuit region 13. The polysilicon layer 14 is patterned to form a floating gate (not shown).
After a high-k dielectric material layer and a metal layer are successively formed on the polysilicon layer 14, the metal layer and the high-k material layer are patterned to form a preliminary control gate 18 and a dielectric layer pattern 16 on the polysilicon layer 14. Since the dielectric layer 16 is formed in the cell region only, it may be desirable to use a hard mask (not shown) to form the dielectric layer 16. If the hard mask is formed using silicon nitride or silicon oxide, the hard mask may react chemically with the dielectric layer pattern 16, which may impair the electrical characteristics of the dielectric layer pattern 16. Therefore, the hard mask may generally be formed using a metal.
However, a hard mask layer formed of metal may be oxidized during an ashing process used for removing a photoresist pattern (which may be used, for example, as an etching mask for forming the preliminary control gate 18). When the hard mask made of metal is oxidized as described above, the interface resistance between the dielectric layer 16 and the preliminary control gate 18 may increase. In addition, the preliminary control gate 18 and/or the hard mask may be lifted away from the dielectric layer 16. Furthermore, it may be desirable to form an additional metal layer in the peripheral circuit region 13 after forming the dielectric layer 16, because the preliminary control gate 18 may be removed in the peripheral circuit region 13 in an etching process used for forming the dielectric layer 16. Thus, processes for forming the dielectric layer 16 and the preliminary control gate 18 may be complicated, because two metallizations may be required to form a control gate 18 in both the cell region 11 and the peripheral circuit region 13.